Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /I3C /I3C_CCC_DEVICE_STATUS

Pending Interrupt This field reflects the value driven on PENDING_INT input port.

Protocol Error This bit is set when the slave controller encouters a Parity/CRC error during write data transfer.

Activity Mode This field reflects the input port signal ACT_MODE.

Underflow Error This bit is set if I3C slave terminates a read transfer because of unavailability of data in the transmit buffer. This is cleared only after master reads the device status through GETSTATUS CCC.

Slave Busy This bit is set if any change is made by the current master in to MRL register or occurance of any error. It is cleared after slave application resumes the slave operation by writing 0x1 in I3C_DEVICE_CTRL[RESUME] field.

Overflow Error Overflow error condition detected during master write transfer. This is cleared only after master reads the device status through GETSTATUS CCC.

Data Not Ready This bit is set when private read request from master is NACKed because of any of the following conditions:

• Command FIFO empty
• Tx FIFO threshold is not met
• Response FIFO full

Buffer Not Available This bit is set when private write request from master is NACKed because of Rx buffer not having I3C_DATA_BUFFER_THLD_CTRL[RX_BUF_THLD] number of empty locations or Response buffer is full. In SDR mode of operation this is cleared when the master issues GETSTATUS CCC or upon space becoming available in the buffer and the successful completion of the next write transfer. In HDR mode of operation it is cleared only when master issues GETSTATUS CCC.

Frame Error This bit is set when private write request from master has frame error in HDR-DDR mode. This is cleared only after master reads the device status through GETSTATUS CCC.